Power devices and power integrated circuits (PICs) have a broad range of applications ranging from automotive electronics and avionics to industrial power control. The primary advantage of PICs is the control of power systems at a lower cost. The cost savings from PICs result from package size reduction, elimination of discrete components, and reduced interconnect requirements. A second advantage of PICs is microprocessor compatibility. By integrating power and logic, PICs can become high voltage or high current input/output (I/O) circuits for the microprocessor.
Before power and logic devices can be integrated, a suitable isolation technology must be chosen to separate the high power devices electrically from the lower power logic. Although many isolation techniques exist, they fit generally into two basic categories: junction isolation and dielectric isolation.
Junction isolation (JI) is accomplished, in a standard bipolar process, by using deep P diffusions in the N-type epitaxial layer for lateral isolation as illustrated in FIG. 1. The lateral isolations are reverse biased by coupling them to the lowest potential in the circuit. JI thus implements reverse biased PN junctions to achieve isolation.
However, certain problems attend implementation of JI technology. As vertical devices are required to handle higher voltages, the epitaxial layer must become thicker to handle larger depletion regions. As the epitaxial layer increases, isolation diffusions must become deeper and wider, due to outdiffusion, making them more difficult to make while reducing circuit density.
Another drawback to JI is the increased leakage current at elevated temperatures, leading to device crosstalk and the potential of forming PNPN latchup circuits. A PNPN latchup circuit is illustrated in FIG. 2. The latchup circuit consists of two parasitic transistors, a PNP transistor T.sub.1 and an NPN transistor T.sub.2, with an effective resistance between the emitter and base of each transistor. The PNPN structure latches up when both transistors enter the active region and the product of the transistors' gains is greater than one.
The transistors can enter the active region if the isolation junction becomes forward biased and the resistors R1 and R2 are large enough to maintain the bias. The bias can occur due to stray currents in the epitaxial layer, voltage spikes in the isolation diffusion, improper sequencing of voltage supplies or displacement currents from rapidly changing node voltages. The resistances R1 and R2 are determined primarily by the doping of the epitaxial layer. As the doping of the epitaxial layer is increased, the resistance of the layer decreases.
When latchup conditions occur, the circuit will be able to sustain a current. When T1 and T2 turn on, T2 draws current from the base of T1, thus increasing the current flow through T1. The increase in T1 current further biases T2, thus increasing the current through T2. This regenerative feedback continues until the circuit destroys itself or is limited by circuit resistance. To remove the condition, power must be removed from the circuit.
Dielectric isolation (DI) is achieved by separating devices with a dielectric material, such as silicon dioxide (SiO.sub.2). The separation of devices from each other and the substrate is typically done with conventional DI, local oxidation isolation (LOCOS), trench isolation, or some form of silicon-on-insulator (SOI) technology.
Conventional DI employs single crystal silicon islands on a polysilicon substrate. An outline of the fabrication of DI structures is illustrated in FIGS. 3a-d. Grooves 10 are etched in the substrate 18, followed by oxidation 12, followed by deposition of polysilicon 14. In the completed device, the polysilicon will become the substrate, and therefore the polysilicon must be made very thick, approximately 200 .mu.m thick. An implant step 16 can be added prior to oxidation and deposition to provide a buried layer in the final structure. After the polysilicon 14 is deposited, the silicon surface 18 is lapped and polished until the SiO.sub.2 isolation is exposed. Processing of conventional devices 22 and circuits in the islands 20 thus formed begins at this point.
Some advantages of conventional DI processing are: complete isolation; reduced substrate capacitance; improved bipolar circuit performance in high radiation environments; reduced leakage currents into the substrate; and the established nature of the DI process, which has matured over a long period of time.
Some disadvantages of conventional DI processing are: higher manufacturing costs and lower yields; poor thermal conductivity through the oxide into the polysilicon substrate, since the thermal conductivities of SiO.sub.2 and polysilicon are much lower than the thermal conductivity of single crystal silicon; the incidence of defects in the silicon island caused by stress induced during polysilicon growth; bowing of the wafer, also caused by polysilicon growth; mechanical polishing tolerance-dependent control of tub thickness; and, limitation of the DI process to 3 and 4 inch wafers.
A variation on the conventional DI process is the Vertical Lateral Composite Structure (VLCS), illustrated in FIGS. 4a-e. Processing of the VLCS structure is identical to the DI process (and so the same reference numerals are used to indicate the various structures), except that windows 24 are etched prior to polysilicon 14 deposition. Upon deposition, the polysilicon 14 crystallizes into single crystal silicon 26 over the exposed silicon island 20. The wafer is then ground and polished as in DI, leaving single crystal islands in contact with an essentially single crystal substrate. Processing of conventional devices and circuits is carried out in the single crystal islands.
Advantages of VLCS over the previously discussed form of DI include better heat dissipation through the single crystal silicon 26 and reduced wafer bowing from polysilicon 14 deposition. The main disadvantage of VLCS is process complexity. The fabrication sequence retains the complex DI process with an added photolithography step.
Local oxidation isolation (LOCOS), anotherprocess employing DI, uses locally oxidized regions to isolate devices. A typical LOCOS process sequence is illustrated in FIGS. 5a-c. A thin, stress relief oxide 30 is grown and a thin layer 32 of silicon nitride (Si.sub.3 N.sub.4) is deposited on the oxide 30. The Si.sub.3 N.sub.4 32 and oxide 30 are then patterned. A thick oxide 34 is then grown on the surface, and the Si.sub.3 N.sub.4 32 layer is removed. As shown, Si.sub.3 N.sub.4 32 masks the underlying silicon 36 from oxidizing. Following the oxidation, Si.sub.3 N.sub.4 32 is selectively etched without affecting the SiO.sub.2 34.
Two main advantages of LOCOS are that it provides a nearly planar structure, and that smaller devices are possible since contact can be made to regions bounded by local oxidation without, an additional contact mask and alignment step. FIG. 6a illustrates the emitter, base, and collector of a conventional planar process and FIG. 6b the emitter, base and collector of a LOCOS process. LOCOS provides better lateral isolation than JI, while reducing sidewall and lateral parasitic capacitances.
LOCOS has some weaknesses. During the thick oxidation step, local oxidation can penetrate under the Si.sub.3 N.sub.4 mask, creating the "bird's beak" 40 and "bird's crest" 42 effects illustrated in FIGS. 7a and b, respectively, thereby reducing the available area for device fabrication. Another problem is caused by the difference in coefficients of thermal expansion between Si.sub.3 N.sub.4 and Si.
Another type of DI is so-called trench isolation. The process flow for trench isolation is illustrated in FIGS. 8a-c. Trenches 44 are formed in the silicon 46 and the trench sidewalls are oxidized 48. The trenches 44 are then filled with polysilicon 50 and etched, making the wafer surface flat to avoid breakage of metallization lines due to step coverage.
Devices 52 are then fabricated between trenches 44, with the trenches 44 providing lateral dielectric isolation. Trench isolation is typically a shallow process designed primarily for high density circuits. However, deep (5-6 .mu.m) trenches have been used to isolate CMOS devices. The deep trenches provide increased circuit density and reduced latch-up susceptibility. The higher circuit density is due to the elimination of the "bird's beak" 40 and "bird's crest" 42 (FIGS. 7a-b) effects seen in LOCOS structures. Although trench isolation provides lateral dielectric isolation, vertical isolation is still JI, and collector-to-substrate capacitance therefore is not significantly reduced.
Silicon-on-insulator (SOI) is another form of DI. Some silicon-on-insulator (SOI) technologies are silicon implanted with oxygen (SIMOX), silicon-on-sapphire (SOS), bonded wafers, oxidation of porous silicon (FIPOS), solid state recrystallization, and epitaxial lateral overgrowth (ELO). SOI technologies reduce leakage currents and eliminate potential PNPN latchup circuits. These technologies are also capable of high voltage operation resulting from the dielectric's ability to block large voltages.
SOI technologies must meet two criteria. First, crystal defects in the film can cause increased leakage current in the circuit, so crystal defects in SOI films must be minimized so that device performance is not degraded. Second, since warpage of the wafer can create defects and cause problems in the lithography process, warpage must be minimized.
The SIMOX process forms a layer of SiO.sub.2 under the surface of the silicon. This is accomplished by implanting a large dose 56 of high energy oxygen ions, as illustrated in FIG. 9a. Higher energies increase the depth at which SiO.sub.2 is formed, but projected and transverse straggle increase with increasing implant energy. This variation in depth and width creates a larger volume of SiO.sub.2, which requires that a larger dose of oxygen ions be implanted. A lower energy and lower dose can be used, but the depth of penetration is reduced. After the oxygen 56 is implanted, the wafer must be annealed (FIG. 9b) to "heal" the implant damage to the surface 58 of the silicon 60 and form SiO.sub.2 62.
This technology improves packing density of circuits, reduces design and fabrication complexity, improves speed and power consumption, and has potential for high voltage applications.
However, SIMOX is currently limited to thin layers 62 of SiO.sub.2 and thin layers 60 of single crystal silicon. This limits SIMOX to low voltage MOS and CMOS device applications. Another problem with SIMOX is the high dose 56 of oxygen required to form the oxide. Ion implanters presently in use require on the order of 10.sup.3 seconds per wafer to implant such a high dose, about 10.sup.18 ions/cm.sup.2. The defect density and higher leakage currents resulting from the heavy implant dosage deter from the use of SIMOX for bipolar applications.
Silicon is fabricated on sapphire (SOS) by growing an epitaxial layer 64 of silicon on a sapphire substrate 66, as illustrated in FIG. 10. The basic advantage of SOS technology is increased packing density due to the simplicity of the isolation scheme. Minimum device spacing is determined by linewidth on the mask and mask alignment. Also, the parasitic capacitances of electrodes are reduced, since the substrate capacitance is nearly eliminated. This feature permits devices constructed using SOS technology to operate at higher frequencies than equivalent circuits in bulk silicon.
However, SOS films tend to be inferior electronically and physically to bulk material. SOS tends to have higher defect density and shorter minority carrier lifetimes than bulk silicon. The defects in the Si film 64 are caused by the differences in atomic spacing of the sapphire 66 and Si 64 crystals. As a result, Si films in SOS technology are effectively limited to 1 .mu.m in thickness. Longer lifetimes are desirable in bipolar devices since current flow in bipolar devices depends on minority carriers. The longer the minority carrier lifetime, the lower the recombination, and hence the greater the forward current gain. Therefore, SOS has been primarily a MOS technology, since minority carrier lifetime is not as critical in MOS devices. Furthermore, the sapphire substrate 66 is much more expensive than a silicon substrate.
Another DI technique is the bonded wafer technique. This is a relatively new approach to SOI and consists of bonding two 70, 72 oxidized 74 silicon 76 wafers together. This is done by placing the oxidized wafers 70, 72 in contact with each other and exposing them to a high temperature oxidizing ambient atmosphere. A bonding oxide forms between them, and one 72 of the wafers is ground and polished to the desired thickness. The process sequence is illustrated in FIGS. 11a-c.
Bonded wafers should provide bulk crystal quality since the isolated layer began as a bulk wafer. Better circuit density than JI is achievable with the addition of the trench isolation process. Isolation oxide thickness is controllable, allowing growth of thick oxide for high voltage applications.
As with conventional DI, the thickness control of the ground and polished wafer is determined by the mechanical tolerances of the machine. This is a problem since over 99% of wafer 72 typically must be removed. A typical tolerance is 11 .mu.m.+-.2 .mu.m across the wafer. Another problem is the bonding of the two wafers 70, 72. If the bond is incomplete or weak, the wafers 70, 72 may not remain bonded throughout subsequent fabrication operations.
Another DI technique is full isolation by porous oxidized silicon (FIPOS). FIPOS takes advantage of an electrochemical reaction forming porous silicon selectively in heavily doped silicon. The original process sequence is illustrated in FIGS. 12a-d. Wafers 80 are placed in hydrofluoric acid (HF) 82 and a current 84 is applied across the heavily doped silicon surface 86 of each wafer 80. This process, called anodization, creates a porous surface 90 on the wafer 80. Once this porous surface 90 is formed, a silicon epitaxy 92 is grown. Islands 94 are then etched in the epitaxy 92, leaving exposed pores 96 filled with silicon between the islands 94. The wafer 80 is oxidized 98, and the porous anodized silicon in the pores 96 oxidizes faster than the epitaxial islands 94, leaving silicon islands 94 on oxide 98.
However, islands 94 of silicon have been observed to fall off the porous oxide surface in subsequent processing steps. This occurs because of the high etch rate of porous oxide compared to the oxide on the islands. The porous oxide etches underneath the islands, essentially disconnecting them from the wafer.
Another type of DI is solid state recrystallization. This process involves recrystallizing a previously deposited layer 100 of silicon on an oxidized 102 wafer 104. The silicon layer 100 is heated to the point at which it will recrystallize, but not melt. The crystal orientation can be controlled by opening a seed window 106 in the oxide 102 to the substrate 104. The deposited silicon 100 will recrystallize in the same orientation as the wafer 104. This process is illustrated in FIGS. 13a-c.
Several sources for heating the silicon layer 100 have been used. These include high powered lasers, electron beams, graphite strip heaters, and arc lamps. These sources heat small zones on the wafer 104, and the source is moved across the wafer 104. This process is also known as zone melt recrystallization (ZMR).
A major problem with this technique is that the temperature differences among the melt zone, substrate, and surrounding film can induce stresses that cause defects in the recrystallized film. High defect densities are, of course, detrimental to device performance.
Another form of DI is epitaxial lateral overgrowth (ELO). ELO is illustrated in FIGS. 14a-c. In ELO, a substrate 110 is oxidized 112, a seed hole 114 is opened, exposing the substrate 110, and silicon 116 is grown epitaxially only on the exposed 114 silicon 110. This is known as selective epitaxial growth (SEG). Once the SEG reaches the surface 118 of the oxide 112 (FIG. 14b), SEG continues to grow vertically, but also starts to grow laterally (FIG. 14c). This lateral growth gives rise to the name ELO.
By combining ELO and trench isolation, SOI films can be formed and devices fabricated. A typical process sequence is illustrated in FIGS. 15a-d. A wafer 120 is oxidized 122, then patterned, and then seed windows 124 are etched around oxide islands 126. Silicon 128 is then selectively grown epitaxially, vertically and laterally, and the lateral overgrowths merge together over the oxide (FIG. 15b). The silicon 128 epitaxy is then planarized, trench 130 isolations are formed and circuits 132 are fabricated in the SOI islands.
This process has the advantages of SOI, and is much less expensive than SOS. However, the process is complex, involving planarization and trench isolation.